This invention relates to a multiple vector processor and, more particularly, to a multiple vector processor in which memory port logic units of main storage are shared.
Multiple vector processing apparatuses having memory ports provided corresponding to their processors are discussed in "A Simulation Study of the CRAY X-MP Memory System" (by T. Cheung and J.E. Smith, IEEE Transactions on Computers Vol. C-35, No. 7, July 1986), "CRAY-2 Super Computer with 2G Bytes Main Storage and Fluid Cooling System" (by K. Terauchi, Nikkei Electronics, Dec. 16, 1985), and European Patent Publication No. 123, 509).
The meaning of the term memory ports used herein differs from that used in conventional general purpose computers. This difference will first be clarified.
In a general purpose computer, the space in main storage is divided into a plurality of partial spaces which are called "memory ports" and which serve as logical units for receiving main storage access requests issued from an instruction processing unit incorporated in the general purpose computer. Therefore, the memory ports are not managed on the basis of "meanings" such as possibility or impossibility of instruction processing. For the instruction processing unit of a general purpose computer, the memory ports are portions for receiving requests for access to main storage, and are always operative.
On the other hand, the above-mentioned memory port logic units are logical circuits having the following functions:
1. a function of generating a series of addresses for reading vector data from or writing vector data into main storage; and
2. a function of effecting the above function in response to a vector instruction (e.g., a vector load instruction).
Therefore, they are not passive units for receiving main storage access requests, like the memory ports of a general purpose computer, but are active units which generate the series of addresses needed to realize the processing operations demanded by an instruction and issue access requests to main storage when they receive an instruction. For this reason, the name "requestor" is often used for a "memory port" of a vector processor. In this description of the present invention, the name "memory port logic unit" will be used so as to follow precedent and at the same time to allow a distinguishment to be made between the present use and use as made with general computers.
Since the operation of a memory port logic unit of a vector processor is defined by an instruction and is started in response to the commencement of the processing of the instruction, a mechanism which manages the state of the memory port logic unit must be provided in the vector processor in order to enable this kind of logical operation. The word "management" is not used herein to mean that memory ports in a general purpose computer "manage" main storage access requests. It represents the "management" which provides one of the factors of a decision as to whether a vector instruction which accesses main storage can be executed in the vector processor at a certain timing.
When a vector processor, or a multiple vector processor constituted by a plurality of vector processing devices, is designed to improve the capacity of vector processing, it is necessary to increase the number of memory port logic units correspondingly.
On the other hand, the logic of main storage needs to be single from restriction imposed by the language specification. The increase in the number of memory port logic units means an increase in the load on the logical unit which determines the priority order of a plurality of memory port logic units relative to one interleaved bank in main storage.
In existing vector processors, the peak data processing speed is in a range in excess of 1 GFLOPS. This means that the data processing speed of a circuit for determining the priority order of memory port logic units must be of the order of gigawords.
If the necessary number of vector arithmetic units are arranged parallel to each other in order to enable a processing speed of the order of 10 GFLOPS by the multiprocessing of the vector processing devices, the processing speed of the vector processing units can be made to reach the desired level. However, it is not possible for circuits for determining the priority order of memory port logic units to be arranged in parallel, and it is therefore difficult to ensure the data processing speed demanded by the vector processing units.
As a result of the fact that a storage control unit have become incapable of following the improvements in processing speed of vector processing units, a certain type of multiple vector processor has been designed to have local memories in vector processing units. If such an architecture is adopted, the throughput of the vector processing units and the main storage device can be made smaller than that of the arrangement using no local memories, but on the other hand, the amount of hardware required for managing data transmission between local memories and the main storage device is increased. In particular, as the number of vector processing devices increases, the amount of hardware required for the data transmission management increases further. Therefore, a multiple vector processor having an architecture in which local memories are each provided in vector processing devices is designed in such a manner that the local memories are indicated in the language specifications and data transmission is effected between the main storage device and the local memories on the user's responsibility. In this system, the amount of hardware is not increased, but the singlestorage hierarchy which has been preserved by the conventional language specification is destroyed. For this reason, the user must make sacrifices concerning the compatibility of programs, facility of algorithm description, and so forth.